A semiconductor integrated circuit such as an LSI (Large Scale Integration) mounted on products such as vehicles, medical devices is required to prevent occurrences of troubles by a system before incurring a serious trouble by performing a failure detection. An idea improving security by mounting a function to reduce a risk when an element constituting the system and a mounted component are failed is called as a functional safety.
A general test method of the LSI is that a test pattern is input to the LSI by using an LSI tester, an output value thereof is taken into the LSI tester, it is compared with an expected value to decide presence/absence of failure. There is a BIST (Built in Self-Test) as one technology for a design for testability (DFT) of the LSI. According to the BIST, it is possible to decide the presence/absence of failure by a single LSI by including a test pattern generation circuit generating the test pattern and an expected value comparison circuit comparing the output value and the expected value in the LSI in advance and performing the test of the LSI. The test of the LSI using the BIST circuit is generally performed before shipping of the LSI.
FIG. 7 is a diagram illustrating a configuration example of a BIST circuit. An LSI 100 having the BIST circuit includes a test object circuit 101, a test pattern generator (TPG) 102, an expected value comparison circuit 103, and a multiplexer 104. A normal input SIN or a test input TIN is input to the test object circuit 101 via the multiplexer 104 controlled by a mode signal TMD from a test mode switching control part 105. In a normal operation, the normal input SIN is input to the test object circuit 101, and in a test operation, the test input TIN being a test pattern generated by the test pattern generator 102 is input to the test object circuit 101. The test object circuit 101 outputs an output value being a process result as a normal output SOUT. In the test operation, the expected value comparison circuit 103 decides the presence/absence of failure by comparing the output value of the test object circuit 101 and the expected value, and outputs a decision result as a test output (admission decision) TOUT.
Besides, a BIST circuit including an expected value generation circuit receiving an output signal from an interface part to a memory circuit and generating an expected value signal, and a comparison decision circuit performing a decision of matching or unmatching by comparing the output signal of the interface part and the expected value signal, and capable of performing a test of the interface part of a memory LSI is proposed (for example, refer to Patent Document 1).
[Patent Document 1] Japanese Laid-open Patent Publication No. 2005-339675
A BIST circuit of the related art is a circuit assumed to perform a test of an LSI when the LSI is before shipping and a test object circuit is in a non-operation state such as in a sleep mode, and it is not assumed to perform the test when the LSI is in actual operation. It is desirable that it is possible to perform the test by using the BIST circuit even in actual operation after the LSI is incorporated in a product or a system from a point of view of functional safety. There is a finite state machine (FSM) being an important component managing a control function as one of logic circuits whose reliability is required in the LSI.